1. Field of the Invention
The present invention relates to radio frequency local oscillator generators used with multiple-mixer tuners.
2. Prior Art
Superheterodyne receivers use one or more local oscillators (LO) to convert an input frequency to an intermediate frequency before the signal is demodulated. In an ideal receiver, these frequency conversions would not distort the input signal and all the information in the input signal would be recovered. In actual application, the local oscillator can add distortions that can limit the receiver's ability to recover the signal information. The principle local oscillator degradation is random phase variations known as phase noise.
The ideal local oscillator (LO) generator for implementing multiple output phases for use in applications such as the commonly assigned U.S. patent application Ser. No. 11/078,050, filed Mar. 11, 2005 entitled “Harmonic suppression mixer and tuner”, incorporated herein by reference, must have low phase noise and there must be a minimum phase mismatch between the multiple outputs. Ideally, the LO generator would use minimum chip area and minimum power.
The minimized phase mismatch between the multiple outputs is required in many applications because of the need for high image rejection and high harmonic rejection in the mixing and tuning process. Multiple frequency division ratios are also needed to provide frequency agility in the tuner.
U.S. Pat. No. 6,856,208, issued to Lee et al. on Feb. 15, 2005, entitled “Multi-phase Oscillator and Multi-phase Oscillation Signal Generation Method”, incorporated herein by reference, describes a multi-phase oscillator that can be a single phase oscillator, a 180 degree phase difference oscillator or a multiple phase difference oscillator.
In applications such as multi-mixer tuners, described in co-pending U.S. patent application Ser. No. 11/078,050, filed Mar. 11, 2005 entitled “Harmonic suppression mixer and tuner”, multiple frequency division ratios are needed in order to generate a wide range of LO output frequencies from a limited input clock frequency range.
The multi-mixer architecture needs multiple LO clock phases to actively reject higher harmonics of the LO clock signal. To do this with high suppression ratios, the low phase mismatch requirement is of the utmost importance.
To reduce overall cost, chip area must be kept as low as possible; furthermore, a more compact layout will result in a lower uncertainty on phase accuracy.
FIG. 1 shows a solution known in the prior art. The slave latch not only provides the LO signal to the mixer, but is also loaded by the master latch in the next flip-flop. This results in a deterioration of the signal slope and phase accuracy. To minimize the deterioration due to capacitive and other loading, an emitter follower or source follower can be included at the output of the slave latch or the bias current of the latch can be increased.
The master input of flip-flop 2 in FIG. 1 is directly connected to the output of flip-flop 1. Any feed-through of the master clock to the input of the master latch of flip-flop 2, results in a ripple on the LO signal going to the mixer. This can result in LO feed-through and down conversion of unwanted RF signals at harmonics of the LO signal. Both effects directly lead to deteriorated harmonic rejection performance of the mixer architecture referred to above.
The propagation delay from the slave output of flip-flop 1 to the master input of flip-flop 2 has to be low enough to meet the setup-time requirement of the slave latch at high frequencies. If this requirement is not met, the phase accuracy of the output signal is deteriorated considerably. The optional emitter/source follower included to solve the load-related issue described above adds additional delay. This delay can be minimized by increasing its bias current, but results in increased circuit power consumption.
The physical layout of the circuit as shown in FIG. 1 poses considerable challenges that need to be solved in order to avoid adverse effects on the performance. Clock lines and slave output lines can couple resulting in unwanted clock feed-through. Additionally, the connection between slave output and master input needs to be kept short to avoid extra loading due to parasitics. The interconnection scheme used at the slave output may be complicated and therefore, layout asymmetry will be unavoidable. If a differential signaling implementation is used, this asymmetry will have a negative influence on the final phase accuracy.
Even by substantially increasing current consumption, not all of these issues can be solved.
FIG. 2 shows another prior art solution where the input of flip-flop 2 is driven with the master latch output of flip-flop 1. This requires the clock signals of flip-flop 1 and flip-flop 2 to be inverted with respect to each other to avoid digital race conditions. For example, flip-flop 1 would be clocked at the rising edge and flip-flop 2 would be clocked at the falling edge of the clock signal. In fact, using the master of flip-flop 1 as a reference, the input latch of flip-flop 2 then can be considered a slave latch since it is clocked on the same clock edge as the slave of flip-flop 1.
A major negative side effect of this clocking scheme is that the resulting output signal phase accuracy becomes dependent on the duty cycle of the clock signal. Furthermore, the propagation delay of the master latch will increase due to increased loading. This can be alleviated but requires increasing the master latch bias current or adding an emitter or source follower.